1. Field of the Invention
The present invention relates to a technology for relaying data from adapters to a controller that includes a processor.
2. Description of the Related Art
In recent years, improved processing ability of computers has resulted in ever increasing volume of data used by the computers. Technologies related to storage of considerable volume of data are being examined. Specifically, for example, one of the technologies called Redundant Array of Independent Disks (RAID) involves combining a plurality of hard disk drives to realize a speedy, highly reliable, and high capacity disk system.
In a disk system such as RAID, a disk array device, which includes a plurality of disks for storing data, receives commands from a host computer and performs data read and data write operation. In this process, the data that is exchanged between the host computer and the disks is cached in a cache memory of the disk array device. Generally, subsequent processes become speedy when the data is read from the cache memory instead of reading the data from the host computer or the disks.
For example, Japanese Patent No. 2567922 discloses a conventional technology in which a plurality of channels is arranged in between a host computer and a disk array device for efficient transfer of data. A plurality of channel adapters in the disk array device is connected to the host computer. In the conventional technology, a plurality of data transfer routes is formed, which includes the respective channel adapters, between a cache memory of the disk array device and the host computer.
When data from the host computer is written to a disk in the disk array device, a switch becomes necessary to transform data transfer routes into one route and to relay the data to the cache memory. The data from the channel adapters and the switch is written to the cache memory via a cache controller that includes a chip set and a central processing unit (CPU), which is shown in FIG. 8A. As shown in FIG. 8A, write-data input from the host computer to the channel adapters is transferred to the chip set in the cache controller via the switch (step S1). A destination address of the write-data is referred to by the chip set, and the write-data is written onto a relevant address in the cache memory (step S2).
In the specification of a peripheral component interconnect (PCI) bus, it is defined that in the ordinary process of the cache controller, an interruption process is executed by the CPU in the cache controller according to an interrupt method called message signaled interrupt (MSI). When a particular address is specified as a destination address of the write-data, the chip set notifies the CPU of occurrence of interruption such that the CPU executes the interruption process according to MSI.
That is, as shown in FIG. 8B, the write-data that requests interruption is transferred to the chip set in the cache controller via the channel adapter and the switch (step S3). The chip set detects if the destination address of the write-data is an MSI address, and prompts the CPU to execute the interruption process (step S4).
When the interruption process is executed according to MSI, a process defined in advance as the interruption process is executed. However, if an error occurs in a write-data that has requested the interruption, or if an error occurs in the destination address of the write-data, a process not defined as the interruption process may be requested.
At such time, the CPU that is requested to execute undefined interruption process judges that an error has occurred and executes an error recovery process. If it is judged that a fatal error has occurred, all processes are suspended. If the CPU in the cache controller suspends the processes, reading or writing of data from or to the disk array device becomes impossible, resulting in considerable loss.
Even if the CPU performs the error recovery process without suspending the processes, the CPU is burdened with the extra processing load for determining a cause of the error. In other words, if there is a request for undefined interruption process, the CPU needs to find out the device from which the error has originated. That is, the CPU needs to check the condition of the channel adapters, the switch, and the chip set in the cache controller, and any other devices that may have caused the error. Thus, the CPU is overburdened and data transfer between the host computer and the cache memory is affected.